This application claims priority from Korean Application No. 2001-18960, filed Apr. 10, 2001, the disclosure of which is hereby incorporated herein by reference.
Various integrated circuit devices include an insulating layer and a conductive layer arranged on an integrated circuit substrate according to a fabrication pattern. Devices such as transistors, capacitors, interconnection layers, and plugs for connecting to interconnection layers, may be formed in this manner. For certain structures, an additional device may be formed on an upper surface of a first, already-formed, integrated circuit device. In such a case, the electrical characteristics of the first formed device may be changed and/or degraded by the later formed device.
An example of a device subject to this problem is a capacitor, such as a metal-insulator-metal (MIM) capacitor. MIM capacitors are widely used in integrated circuit devices. As is well known to those having skill in the art, a MIM capacitor comprises spaced apart first (lower) and second (upper) metal layers (electrodes) and a dielectric layer therebetween. As the integration density of integrated circuit devices continues to increase, the area occupied by an individual device may continue to decrease. Thus, in MIM capacitors, it may be desirable to increase the capacitance by increasing the effective area of the capacitor, by forming a thin dielectric layer and/or by forming the dielectric layer of a material having high dielectric constant. Furthermore, in order to increase the effective area of a capacitor, the capacitor may be formed to have a three-dimensional structure, such as a fin structure, a cylinder structure and/or a trench structure. Unfortunately, a thin film dielectric may produce decreased reliability and high dielectric constant dielectrics may require new manufacturing processes.
The lower electrodes of a MIM capacitor may be formed of noble metals, such as platinum (Pt), ruthenium (Ru), iridium (Ir), and their oxides which generally do not react with the dielectric layer and have a high work function value. As Ru, in particular, can be easily etched by plasma containing oxygen and can form conductive oxides, Ru often may be used in forming the lower electrode of a MIM capacitor. The lower electrode of a MIM capacitor may be formed to have a three-dimensional structure, such as a cylinder structure, a pin structure and/or a trench structure.
In order to obtain a high dielectric constant from the MIM capacitor, the dielectric layer may be crystallized, for example, by annealing at a temperature above the crystallization temperature, after forming the dielectric layer, and/or the MIM capacitor may be cured by heat-treating the MIM capacitor after forming the upper electrode. In order to reduce defects occurring during processes for forming a capacitor, after forming the capacitor, curing may be performed at a temperature lower than a crystallization temperature, that is, at about 400xc2x0 C., in an oxygen atmosphere. However, the dielectric layer may crack due to heat treatment. Thus, there may be limitations in the heat treatment, and the characteristics of a capacitor may be degraded due to the heat treatment.
Various problems associated with MIM capacitors will now be described further with reference to FIGS. 1A and 1B, FIGS. 2A and 2B, and FIGS. 3 and 4. FIGS. 1A and 1B illustrate a capacitor in which ruthenium (Ru) is used as the metal for the lower and upper electrode, and tantalum oxide (TaOx) is used as a dielectric layer. FIGS. 2A and 2B illustrate the capacitor of FIGS. 1A and 1B after the dielectric layer has crystallized by annealing the lower electrode in a nitrogen (Nx) atmosphere at 700xc2x0 C. for about 30 minutes. As shown in the figures, the lower electrode, which is formed of metals, and the dielectric layer are sequentially formed. An annealing process for crystallizing the dielectric layer is subsequently carried out. As a result, surface roughness of the metal used as the lower electrode may be increased, variations in morphology may occur, and fine cracks may be caused in the dielectric layer during cooling after annealing due to a difference in the thermal expansion coefficient of the dielectric layer and the metal used for the lower electrode. The morphology of the upper electrode and/or the lower electrode of the MIM capacitor may be changed after annealing and/or other heating processes, such as curing in a subsequent thermal treatment, because the grains of the metal for the lower electrode and/or the upper electrode may grow larger in the subsequent thermal treatment.
Further processing of the capacitor may include high-temperature heating during an intermetal dielectric (IMD) deposition or an interconnection process following formation of the upper electrode. A curing step may also be used, which may cause further variations in the upper electrode surface roughness and/or morphology. Thermal expansion coefficient differences between the upper electrode IMD, and/or interconnection materials may then cause similar problems to those discussed relative to the lower electrode. By way of example, a capacitor may be formed using Ru as the metal for a lower and upper electrode and TaOx as a dielectric layer. The capacitor may be annealed in a nitrogen atmosphere at a temperature of about 600-700xc2x0 C. for about 30 minutes before subsequent processing. Such a capacitor is shown in FIG. 3, where the morphology of the upper electrode, as well as that of the lower electrode, has been changed by subsequent high-temperature heating.
As shown in FIG. 4, the leakage current in the capacitor shown in FIG. 3 may be increased by fine cracks in the dielectric layer caused by variations in the surface morphology of the upper electrode and/or the lower electrode. In addition, the adhesive strength of an insulating layer contacting an electrode may be reduced by variations in the surface morphology of the electrode. This could cause the electrode to be stripped from the insulating layer. Such a stripping or flaking problem may be found with contact plugs or interconnection layers as well as capacitors.
Embodiments of the present invention include methods for manufacturing an integrated circuit device. A metal layer is formed on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer covered with the capping layer is heat-treated. The capping layer is removed and the metal layer, which is exposed by removal of the capping layer, is plasma-treated.
In other embodiments of the present invention, a dielectric layer is formed on the plasma treated metal layer opposite the integrated circuit substrate. The formed dielectric layer is heat-treated, for example, to crystallize the dielectric layer. Heat-treating of the metal layer and heat-treating of the formed dielectric layer may be performed in a nitrogen atmosphere at between about 500xc2x0 C. and about 800xc2x0 C. or at about 700xc2x0 C. As a result of the pre-heating and plasma-treating the metal layer may substantially retain its surface morphology during heat-treating of the formed dielectric layer.
In further embodiments of the present invention, the capping layer is an oxide layer. The plasma-treating of the metal layer may include exposing the metal layer to a plasma containing argon (Ar) and/or nitrogen (N2). The integrated circuit device may be an integrated circuit capacitor and the metal layer may be an electrode of the capacitor and the dielectric layer may be a dielectric layer of the capacitor.
In other embodiments of the present invention, the metal layer is formed from at least one of ruthenium (Ru), iridium (Ir), platinum (Pt), rhodium (Rh), palladium (Pd), and metal oxides of Ru, Ir, Pt, Rh, and Pd. The dielectric layer may be an oxide layer formed of tantalum (Ta), titanium (Ti), and/or aluminum (Al). In yet other embodiments, the dielectric layer may be formed of at least one of SrTiO3 (STO), (Ba, Sr)TiO3 (BST), PbTiO3, Pb(Zr, Ti)O3 (PZT), SrBi2Ta2O5 (SPT), (Pb, La)(Zr, Ti)O3, Bi4Ti3O12, and BaTiO3 (BTO).
In further embodiments of the present invention, methods are provided for manufacturing an integrated circuit device including forming a metal layer on an integrated circuit substrate. A capping layer is formed on the metal layer opposite the integrated circuit substrate. The metal layer, covered with the capping layer, is heat-treated. The capping layer is removed and a dielectric layer is formed on the heat-treated metal layer opposite the integrated circuit substrate. The formed dielectric layer is heat-treated, for example, to crystallize the dielectric layer.